Dual Voltage Controlled Gate Delay of Andrew Fitch
Dual Voltage Controlled Gate Delay of Andrew Fitch
Description
This module is a dual VC gate delay. Using CV or the panel pot, delay can be set from 7ms to 1 minute; longer times can be obtained by replacing the 1uF caps with larger values, say 10uF. The output gate signal is on only if the incoming signal is still on. When the incoming gate finishes the output finishes. Technically this module only delays the start/rising edge of the incoming gate.
Files
| Title | Version | Creation date | Copyright notice | Software | Download link |
|---|---|---|---|---|---|
|
Плата (оригинальная версия)
Плата (оригинальная версия) |
0.9 | 2/22/2019 | Эндрю Фитч | DipTrace Schematics | Download PDF |
|
Панель (оригинальная версия)
Панель (оригинальная версия) |
0.9 | 2/22/2019 | Эндрю Фитч | DipTrace Schematics | Download PDF |
Bill of materials
| # | Value | Quantity | Designator | Comment |
|---|---|---|---|---|
| Semiconductors | ||||
| 1 | 1N4148 | 4 | D1, D2, D3, D4 | |
| 2 | BC557 | 4 | Q1, Q2, Q3, Q4 | |
| 3 | TL072 | 2 | U1, U2 | |
| Resistors | ||||
| 1 | 10k | 10 | R1, R10, R15, R16, R17, R19, R2, R24, R26, R9 | |
| 2 | 2k | 8 | R11, R12, R18, R20, R21, R22, R7, R8 | |
| 3 | 100k | 8 | R13, R14, R23, R25, R3, R4, R5, R6 | |
| Capacitors | ||||
| 1 | 1uF/25V | 2 | C1, C2 | |
| 2 | 10uF/25V | 2 | C3, C8 | |
| 3 | .1uF | 4 | C4, C5, C6, C7 | |
| Inductances | ||||
| 1 | Bead | 2 | L1, L2 | |
| Other | ||||
| 1 | 2.54/2P | 7 | J1, J2, J3, J4, J5, J6, J8 | |
| 2 | 3.96-3P | 1 | J7 | |
| # | Value | Quantity | Designator | Comment |
|---|---|---|---|---|
| Semiconductors | ||||
| 1 | Red LED | 4 | D1, D2, D3, D4 | |
| Other | ||||
| 1 | Jack In | 6 | J1, J11, J12, J2, J7, J8 | |
| 2 | 2.54/2P Female | 7 | J10, J13, J3, J4, J5, J6, J9 | |
| 3 | 100k/Lin | 4 | RV1, RV2, RV3, RV4 | |