Gate and Trigger generators/processors

Gate to Trigger converter of Harald Antes

Quadruple rising positive signal edge to trigger converter

Description

Gate to Trigger of Harald Antes

Project schematics / Gate to Trigger converter of Harald Antes
Title	Version	Creation date	Copyright notice	Software	Download link
Version 0.9 The original schematics and circuit description here	0.9	12/24/2018	Harald Antes	DipTrace Schematics	Download PDF
Панель (оригинальная версия) Панель (оригинальная версия)	0.9	4/2/2019	Харальд Антес	DipTrace Schematics	Download PDF

Плата (оригинальная версия)
#	Value	Quantity	Designator	Comment
Semiconductors
1	1N4148	8	D1, D2, D3, D4, D5, D6, D7, D8
2	TL074	2	U1, U2
Resistors
1	1M	4	R1, R10, R19, R28
2	47K	4	R11, R2, R20, R29
3	100K	8	R12, R13, R21, R22, R3, R30, R31, R4
4	15K	4	R14, R23, R32, R5
5	10K	4	R15, R24, R33, R6
6	7K5	4	R16, R25, R34, R7
7	75K	4	R17, R26, R35, R8
8	330R	4	R18, R27, R36, R9
Capacitors
1	*	4	C1, C2, C3, C4	C1: 10nF = 0.8mS, 15nF = 1.2mS, 22nF = 1.8mS, 33nF = 2.7mS, C2: 10nF = 0.8mS, 15nF = 1.2mS, 22nF = 1.8mS, 33nF = 2.7mS, C3: 10nF = 0.8mS, 15nF = 1.2mS, 22nF = 1.8mS, 33nF = 2.7mS, C4: 10nF = 0.8mS, 15nF = 1.2mS, 22nF = 1.8mS, 33nF = 2.7mS
2	10uF	2	C100, C101
3	.1uF	6	C102, C103, C5, C6, C7, C8
Inductances
1	Bead	2	L1, L2
Other
1	2.54/2P	4	J1, J2, J3, J4
2	3.96-3P	1	J5